I'm

CHANDAN
SAI PAVAN PADALA

Embedded Systems Engineer & VLSI Architect

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High-performance embedded architecture, ultra-low-power 45nm VLSI circuits, and real-time autonomous systems engineered for deterministic reliability.

PicoRV32 + ARM7CPU Architecture
50.00 MHzCore Clock Domain · 12.5 MHz CDC
45nm CMOSAnalog Comparator · 0.115 ps/°C
+56.2%Power Reduction Optimization
Lab Telemetry & Engineering Profile

System Architecture

Electronics and Communication Engineering student with a strong foundation in embedded systems, IoT, and real-time system design. Hands-on experience with ARM-based microcontrollers and signal processing applications. Focused on applying hardware–software integration to engineer innovative solutions in automation, embedded security, and intelligent systems.

10+Silicon & Embedded Systems
9Protocol & Architecture Certs
3+Years Low-Level Engineering
4Hackathons & Autonomous R&D
Telemetry Timeline · Academic & Research Milestones
UNDERGRADUATE · ACTIVE NODEONLINE & DEPLOYING
2023 - Present

B.Tech in Electronics & Communication Engineering

Amrita Vishwa Vidyapeetham, Kasavanahalli, Bengaluru

▹Core focus on Embedded Systems, VLSI Design, Computer Architecture, and Real-Time RTOS.
▹Designed dual-clock RISC-V SoC with CDC handshake bridge and 45nm low-power dynamic comparator.
▹President/Lead of robotics hardware integration; autonomous ADAS testing and radar signal telemetry.
Cadence VirtuosoSystemVerilog/VerilogARM Cortex / LPC2148FreeRTOSMicrowave Radar
SENIOR SECONDARY · VERIFIEDSYNCHRONIZED
March 2023

Intermediate Education

Narayana Junior College, Nallakunta, Hyderabad

▹Intensive focus on Mathematics, Classical Physics, Electromagnetism, and Semiconductor Devices.
▹Strong analytical foundation in differential equations, Fourier analysis, and circuit theory.
Calculus & Linear AlgebraElectromagnetismSemiconductor PhysicsOptics
FOUNDATIONAL · ARCHIVEDVERIFIED MILESTONE
May 2021

Secondary Education

Narayana Concept School, West Marredpally, Hyderabad

▹Formative foundation in science, computer science fundamentals, and basic algorithmic logic.
Fundamental SciencesLogic & MathematicsIntroductory Computing
Hardware Registers & Low-Level Protocols

Silicon & System Capabilities

AGY-SILICON-2026REV 4.2 · ARM7 + RISC-V
PROGRAMMING LANGUAGESFREQ: 50.00 MHz · BUS: APB3
CORE VOLTAGE3.3V / 1.8V DUAL
INTERRUPT LATENCY<12 CYCLES
CDC SYNC STAGES2-FLIP-FLOP
REGISTER INTERFACE · PROGRAMMING LANGUAGES
Assembly Language
Embedded C
C
C++
Python
SPI (Serial Peripheral Interface)
25 MHz Full-Duplex

Active-low CS chip select, synchronous master-out/slave-in high-throughput stream.

CS_EN
CHIP SELECT
SCK_CLK
SYNC CLK
MOSI
PAYLOAD
Interactive Engineering Showcases

Flagship Hardware & Software

All 17 Projects Matrix
Web Serial API · Digital Logic ProbesPresent

Web-Based Digital IC Tester

Built a futuristic web application for mobile IC testing using Web Serial API for reliable hardware communication.

250 MS/sSample RateMicrosecond resolution
0 DriversWeb SerialNative browser interface
50+ ICsLogic DatabaseTTL & CMOS auto-verify
Web Serial APIJavaScript (ES6+)HTML5/CSS3ArduinoEmbedded C
45nm RISC-V SoC · APB3 CDC Bridge · SVA VerifiedJuly 2026

MicroRiv SoC

Designed a dual-clock RISC-V System-on-Chip (SOC) (50 MHz CPU domain / 12.5 MHz peripheral domain) that combines a PicoRV32 core with custom APB3 peripherals (UART, GPIO, countdown Timer) and 16KB system SRAM.

50 / 12.5 MHzDual ClockCPU / Peripheral domain
-90%Dynamic PowerICG latch clock gating
2-StageCDC HandshakeZero-metastability bridge
PicoRV32 RISC-VVerilog/SystemVerilogAPB3 BusClock Domain Crossing (CDC)SystemVerilog Assertions (SVA)Yosys
Dual-Clock CDC & Eye DiagramLIVE SIM
Firmware Reverse Engineering · Headless GhidraJuly 2026

BININO

Designed a browser based firmware extraction toolkit which uses the Web Serial API to create efficient bridges with 50+ microcontroller variants, without requiring local driver installations.

50+ MCUsSupported ChipsAVR, STM32, ESP32, ARM
3-PaneIDE ExplorerReal-time decompilation
<1.2sDecompile CycleHeadless pipeline
Web Serial APIGhidra HeadlessReactGemini APINode.jsAssembly/C
Embedded AI · Multi-File RTOS GeneratorJune 2026

FirmForge

Created an enterprise-level “EmbeddedPilot” engine using streaming Google Gemini API models to generate production-ready peripheral drivers and complex multi-file RTOS architectures directly from natural language specifications.

Multi-TaskRTOS GeneratorTasks, queues, mutexes
100% MISRAC ComplianceProduction-ready drivers
InstantSupabase URLsCollaborative cloud vaults
Gemini APIReact/ViteRTOS/FreeRTOSEmbedded CSupabaseTailwind CSS
Robotics Kinematics · Three.js SimulationMay 2026

JINX - Joint Inverse N-dimensional eXplorer

Developed "JINX", an open-source 3D robotic simulator with real-time kinematics, trajectory planning and interactive environments for multi-DOF robots, using Three.js and Vite.

60 FPSTelemetry LinkBroadcastChannel API
6-DOFJacobian IKReal-time numerical solver
<5msTab Sync DelayIsolated Math Dashboard
Three.jsViteBroadcastChannel APIChart.jsGSAPGitHub Pages CI/CD
Kinematics & Coordinate TrajectoryLIVE SIM
Verified Credentials & Specializations

Certifications

All 10 Certifications
Peer-Reviewed IEEE Publications

Research & Silicon Publications

Accepted for Presentation · December 2026
Robotics & Kinematics

Design and Real-Time Simulation of a 3-DOF RRR Occlusion-Avoidance Robotic Desk Lamp

2nd IEEE International Conference on Robotics and Mechatronics (ICRM 2026)

Closed-Form IKKinematics Enginedual elbow configurations
60 FPSDigital TwinThree.js WebGL simulation
TrapezoidalTrajectoryLagrangian joint dynamics
AcceptedStatuspresentation at IEEE ICRM 2026

▹Modeled forward kinematics using Denavit-Hartenberg parameters and derived a closed-form geometric inverse kinematics solver for dual elbow configurations.

▹Formulated an analytical 3x3 Jacobian for singularity detection, computed Lagrangian dynamics for joint torques, and shaped trajectories with trapezoidal velocity profiling.

▹Engineered an interactive 60 FPS Three.js web-based digital twin simulator integrating top-down vision tracking and noise propagation sensitivity analysis.

Accepted for Presentation · December 2026
Embedded Edge AI & Robotics

A Vision-Based Low-Cost ADAS Validation Platform Utilizing Distributed Master-Slave Architecture on a 1:10 Scale Prototype

2nd IEEE International Conference on Robotics and Mechatronics (ICRM 2026)

> 20 FPSVision InferenceINT8 MobileNetV2 + OpenCV
< ±15 pxTracking Errorlane center tracking accuracy
WebSocketComms Architectureasynchronous master-slave WiFi
EKF FusionState EstimationIMU + wheel encoder odometry

▹Architected a 1:10 scale autonomous vehicle testbed with asynchronous WiFi WebSocket communication between a Raspberry Pi 4B (perception) and ESP32 (motor control).

▹Interleaved classical OpenCV lane detection with INT8-quantized MobileNetV2 traffic sign recognition, sustaining over 20 FPS with an under ±15 pixel tracking error.

▹Implemented an Extended Kalman Filter (EKF) for IMU-encoder odometry fusion and built a priority decision manager with six safety validation checks.

IEEE Xplore / Scopus Indexed · June 2026
VLSI & Analog IC Design

A Low-Power Delay-Optimized High-Speed Dynamic Comparator with Temperature Compensation

2026 IEEE 6th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)

56.22%Power Reductionvs. conventional designs
0.115 ps/°CDelay Sensitivityisothermal stability
45-nm CMOSProcess NodeCadence Virtuoso
-40°C to 120°CThermal Rangeextreme temperature span

▹Engineered a novel hybrid dynamic comparator combining a high-gain cascode cross-coupled preamplifier and simplified latch to drastically cut energy dissipation.

▹Implemented and validated in 45-nm CMOS technology in Cadence Virtuoso and Spectre Simulator across an extensive thermal range from -40°C to 120°C.

▹Achieved a 56.22% reduction in power consumption and near-zero delay sensitivity of 0.115 ps/°C compared to prior temperature-compensated architectures.

▹Solves critical delay variability in SAR and Flash ADCs for next-generation edge devices, wireless communication transceivers, and mobile IoT sensors.

Direct Communications Channel

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INTERACTIVE EXPERIMENT

AstroDither Visualizer

Interactive audio-reactive 3D fluid & dithering simulation built with WebGPU & Three.js TSL.

DIRECT COMMUNICATIONS

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Open to discussions regarding embedded systems engineering, VLSI circuit design, and full-time technical roles.

Building the future, one circuit at a time