Electronics and Communication Engineering student with a strong foundation in embedded systems, IoT, and real-time system design. Hands-on experience with ARM-based microcontrollers and signal processing applications. Focused on applying hardware–software integration to engineer innovative solutions in automation, embedded security, and intelligent systems.
CHANDAN
SAI PAVAN PADALA
Embedded Systems Engineer & VLSI Architect
High-performance embedded architecture, ultra-low-power 45nm VLSI circuits, and real-time autonomous systems engineered for deterministic reliability.
System Architecture
B.Tech in Electronics & Communication Engineering
Amrita Vishwa Vidyapeetham, Kasavanahalli, Bengaluru
Intermediate Education
Narayana Junior College, Nallakunta, Hyderabad
Secondary Education
Narayana Concept School, West Marredpally, Hyderabad
Silicon & System Capabilities
Active-low CS chip select, synchronous master-out/slave-in high-throughput stream.
Flagship Hardware & Software
MicroRiv SoC
Designed a dual-clock RISC-V System-on-Chip (SOC) (50 MHz CPU domain / 12.5 MHz peripheral domain) that combines a PicoRV32 core with custom APB3 peripherals (UART, GPIO, countdown Timer) and 16KB system SRAM.
BININO
Designed a browser based firmware extraction toolkit which uses the Web Serial API to create efficient bridges with 50+ microcontroller variants, without requiring local driver installations.
FirmForge
Created an enterprise-level “EmbeddedPilot” engine using streaming Google Gemini API models to generate production-ready peripheral drivers and complex multi-file RTOS architectures directly from natural language specifications.
JINX - Joint Inverse N-dimensional eXplorer
Developed "JINX", an open-source 3D robotic simulator with real-time kinematics, trajectory planning and interactive environments for multi-DOF robots, using Three.js and Vite.
Certifications
Research & Silicon Publications
A Low-Power Delay-Optimized High-Speed Dynamic Comparator with Temperature Compensation
2026 IEEE 6th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)
▹Engineered a novel hybrid dynamic comparator combining a high-gain cascode cross-coupled preamplifier and simplified latch to drastically cut energy dissipation.
▹Achieved a 56.22% reduction in power consumption and near-zero delay sensitivity of 0.115 ps/°C compared to prior temperature-compensated architectures.
Get In Touch
AstroDither Visualizer
Interactive audio-reactive 3D fluid & dithering simulation built with WebGPU & Three.js TSL.
Connect Directly
Open to discussions regarding embedded systems engineering, VLSI circuit design, and full-time technical roles.
Building the future, one circuit at a time